cys tech electronics corp. s pec. no. : c358 s3 issued date : 20 04.03.09 revised date :20 12.07.19 page no. : 1/6 dtc1 1 5ts3 c y s t ek product s pecification npn digital transistors (built-in resistors) DTC115TS3 features ? built-in bias resistors enable the co nfiguration of an inverter circu it without connecting external input resistors (see equivalent circuit). ? the bias resistors consist of thin -film resistors with complete isolat ion to allow negative biasing of the input. they also have the advantage of almost completely eliminating parasitic effects. ? only the on/off conditions need to be set for operation, making device design easy. ? complements the dta115ts3. ? pb-free & halogen-free package. equivalent circuit outline DTC115TS3 r1 b c e r1=100 k b base c collector e emitter sot-323 c b e absolute maximum ratings (ta=25 c) parameter symbol lim its unit collecto r -b ase v o ltage v cbo 50 v collector-emitter voltage v ceo 50 v emitter-base voltage v ebo 5 v collector current i c 100 ma power dissipation pd 200 mw junction temperature tj 150 c storage temperature tstg -55~+150 c http://
cys tech electronics corp. s pec. no. : c358 s3 issued date : 20 04.03.09 revised date :20 12.07.19 page no. : 2/6 dtc1 1 5ts3 c y s t ek product s pecification electrical characteristics (ta=25 c) parameter symbol min. typ. max. unit test conditions collector-base breakdown voltage v cbo 50 - - v i c =50 a collector-emitter breakdown voltage v ceo 50 - - v i c =1ma emitter-base breakdown voltage v ebo 5 - - v i e =50 a collector-base cutoff current i cbo - - 0.5 a v cb =50v emitter-base cutoff current i ebo - - 0.5 a v eb =4v collector-emitter saturation voltage v ce(sat) - - 0.3 v i c =1ma, i b =0.1ma dc current gain h fe 100 - 600 - v ce =5v, i c =1ma input resistance r 70 100 130 k - transition frequency f t - 250 - mhz v ce =10v, i c =5ma, f=100mhz * * transition frequency of the devic e ordering information device package shipping marking DTC115TS3 sot-323 (pb-free & halogen-free package ) 3000 pcs / tape & reel 8u
cys tech electronics corp. s pec. no. : c358 s3 issued date : 20 04.03.09 revised date :20 12.07.19 page no. : 3/6 dtc1 1 5ts3 c y s t ek product s pecification characteristic curves curre nt g a i n vs c ol l e c t or c urre nt 10 100 1000 0. 1 1 10 100 c o l l e c t o r c u rre n t ---ic (ma ) current gain--- hfe hfe@vce=5v s a t u ra t i on v o l t a g e vs c ol l e c t or c urre nt 10 100 1000 0. 1 1 10 100 c o l l e c t o r c u rre n t --- ic (ma ) saturation voltage---(mv) vcesat@ic=10ib vcesat@ic=20ib p o w e r d e ra t i ng c u rve 0 50 100 150 200 250 0 50 100 150 200 a m b i e n t t e mp e r a t u r e --- t a ( ) power dissipation---pd(mw)
cys tech electronics corp. s pec. no. : c358 s3 issued date : 20 04.03.09 revised date :20 12.07.19 page no. : 4/6 dtc1 1 5ts3 c y s t ek product s pecification reel dimension carrier tape dimension
cys tech electronics corp. s pec. no. : c358 s3 issued date : 20 04.03.09 revised date :20 12.07.19 page no. : 5/6 dtc1 1 5ts3 c y s t ek product s pecification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cys tech electronics corp. s pec. no. : c358 s3 issued date : 20 04.03.09 revised date :20 12.07.19 page no. : 6/6 dtc1 1 5ts3 c y s t ek product s pecification sot-323 dimension *: typical inches he e a a1 q lp e1 e bp 12 3 d w b v a z detail z a c 0 12 sc a l e mm style: pin 1.base 2.emitter 3.collector 3-l ead sot - 323 plasti c surface mou n ted packa g e cys t ek pa ckage code: s3 marking: te 8u device code date code millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.0315 0.0433 0.80 1.10 e1 0.0256* 0.65* a1 0.0000 0.0039 0.00 0.10 he 0.0787 0.0965 2.00 2.45 bp 0.0118 0.0157 0.30 0.40 lp 0.0059 0.0181 0.15 0.46 c 0.0031 0.0098 0.08 0.25 q 0.0051 0.0091 0.13 0.23 d 0.0709 0.0866 1.80 2.20 v 0.0079 - 0.2 - e 0.0453 0.0531 1.15 1.35 w 0.0079 - 0.2 - e 0.0472 0.0551 1.20 1.40 0 10 0 10 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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